Static Timing Analysis

Project : PWM_LED
Build Time : 03/31/15 18:12:48
Device : CY8C4245PVI-482
Temperature : -40C - 85C
VDDA : 5.00
VDDD : 5.00
Voltage : 5
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz N/A
Clock_1 CyHFCLK 24.000 kHz 24.000 kHz 51.062 MHz
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CySYSCLK CySYSCLK 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41666.7ns(24 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\PWM_2:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 51.062 MHz 19.584 41647.083
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ \PWM_2:PWMUDB:sP8:pwmdp:u0\/clock \PWM_2:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.850
datapathcell2 U(1,0) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ \PWM_2:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 4.214
datapathcell2 U(1,0) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 56.844 MHz 17.592 41649.075
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,0) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.850
datapathcell1 U(0,0) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.222
datapathcell1 U(0,0) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_2:PWMUDB:runmode_enable\/q \PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 66.671 MHz 14.999 41651.668
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,0) 1 \PWM_2:PWMUDB:runmode_enable\ \PWM_2:PWMUDB:runmode_enable\/clock_0 \PWM_2:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_2:PWMUDB:runmode_enable\ \PWM_2:PWMUDB:runmode_enable\/q \PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.229
datapathcell2 U(1,0) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 66.676 MHz 14.998 41651.669
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,0) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.228
datapathcell1 U(0,0) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_2:PWMUDB:status_0\/main_1 82.034 MHz 12.190 41654.477
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ \PWM_2:PWMUDB:sP8:pwmdp:u0\/clock \PWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \PWM_2:PWMUDB:cmp1_less\ \PWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_2:PWMUDB:status_0\/main_1 3.000
macrocell11 U(1,0) 1 \PWM_2:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
\PWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_2:PWMUDB:prevCompare1\/main_0 82.109 MHz 12.179 41654.488
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ \PWM_2:PWMUDB:sP8:pwmdp:u0\/clock \PWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \PWM_2:PWMUDB:cmp1_less\ \PWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_2:PWMUDB:prevCompare1\/main_0 2.989
macrocell9 U(1,0) 1 \PWM_2:PWMUDB:prevCompare1\ SETUP 3.510
Clock Skew 0.000
\PWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_22/main_1 82.919 MHz 12.060 41654.607
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ \PWM_2:PWMUDB:sP8:pwmdp:u0\/clock \PWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \PWM_2:PWMUDB:cmp1_less\ \PWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_22/main_1 2.870
macrocell1 U(0,0) 1 Net_22 SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_35/main_1 85.281 MHz 11.726 41654.941
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,0) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_35/main_1 2.536
macrocell2 U(0,0) 1 Net_35 SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 85.339 MHz 11.718 41654.949
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,0) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 2.528
macrocell5 U(0,0) 1 \PWM_1:PWMUDB:prevCompare1\ SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 85.339 MHz 11.718 41654.949
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,0) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 2.528
macrocell7 U(0,0) 1 \PWM_1:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\PWM_1:PWMUDB:status_0\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_0 1.509
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,0) 1 \PWM_1:PWMUDB:status_0\ \PWM_1:PWMUDB:status_0\/clock_0 \PWM_1:PWMUDB:status_0\/q 1.250
Route 1 \PWM_1:PWMUDB:status_0\ \PWM_1:PWMUDB:status_0\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_0 2.259
statusicell1 U(0,0) 1 \PWM_1:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_2:PWMUDB:status_0\/q \PWM_2:PWMUDB:genblk8:stsreg\/status_0 1.515
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,0) 1 \PWM_2:PWMUDB:status_0\ \PWM_2:PWMUDB:status_0\/clock_0 \PWM_2:PWMUDB:status_0\/q 1.250
Route 1 \PWM_2:PWMUDB:status_0\ \PWM_2:PWMUDB:status_0\/q \PWM_2:PWMUDB:genblk8:stsreg\/status_0 2.265
statusicell2 U(1,0) 1 \PWM_2:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_2:PWMUDB:prevCompare1\/q \PWM_2:PWMUDB:status_0\/main_0 3.475
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(1,0) 1 \PWM_2:PWMUDB:prevCompare1\ \PWM_2:PWMUDB:prevCompare1\/clock_0 \PWM_2:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM_2:PWMUDB:prevCompare1\ \PWM_2:PWMUDB:prevCompare1\/q \PWM_2:PWMUDB:status_0\/main_0 2.225
macrocell11 U(1,0) 1 \PWM_2:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 3.478
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,0) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.228
datapathcell1 U(0,0) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\PWM_2:PWMUDB:runmode_enable\/q \PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 3.479
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,0) 1 \PWM_2:PWMUDB:runmode_enable\ \PWM_2:PWMUDB:runmode_enable\/clock_0 \PWM_2:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_2:PWMUDB:runmode_enable\ \PWM_2:PWMUDB:runmode_enable\/q \PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.229
datapathcell2 U(1,0) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 3.482
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,0) 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/clock_0 \PWM_1:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 2.232
macrocell7 U(0,0) 1 \PWM_1:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:genblk8:stsreg\/status_2 3.501
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,0) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.270
Route 1 \PWM_1:PWMUDB:tc_i\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:genblk8:stsreg\/status_2 2.231
statusicell1 U(0,0) 1 \PWM_1:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 Net_35/main_0 4.312
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,0) 1 \PWM_1:PWMUDB:genblk1:ctrlreg\ \PWM_1:PWMUDB:genblk1:ctrlreg\/clock \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 2.040
Route 1 \PWM_1:PWMUDB:control_7\ \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 Net_35/main_0 2.272
macrocell2 U(0,0) 1 Net_35 HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 4.312
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,0) 1 \PWM_1:PWMUDB:genblk1:ctrlreg\ \PWM_1:PWMUDB:genblk1:ctrlreg\/clock \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 2.040
Route 1 \PWM_1:PWMUDB:control_7\ \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 2.272
macrocell6 U(0,0) 1 \PWM_1:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\PWM_2:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_2:PWMUDB:runmode_enable\/main_0 4.619
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,0) 1 \PWM_2:PWMUDB:genblk1:ctrlreg\ \PWM_2:PWMUDB:genblk1:ctrlreg\/clock \PWM_2:PWMUDB:genblk1:ctrlreg\/control_7 2.040
Route 1 \PWM_2:PWMUDB:control_7\ \PWM_2:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_2:PWMUDB:runmode_enable\/main_0 2.579
macrocell10 U(1,0) 1 \PWM_2:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
Net_22/q Pin_1(0)_PAD 27.961
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(0,0) 1 Net_22 Net_22/clock_0 Net_22/q 1.250
Route 1 Net_22 Net_22/q Net_38/main_1 2.252
macrocell3 U(0,0) 1 Net_38 Net_38/main_1 Net_38/q 3.350
Route 1 Net_38 Net_38/q Pin_1(0)/pin_input 5.659
iocell1 P0[6] 1 Pin_1(0) Pin_1(0)/pin_input Pin_1(0)/pad_out 15.450
Route 1 Pin_1(0)_PAD Pin_1(0)/pad_out Pin_1(0)_PAD 0.000
Clock Clock path delay 0.000