\PWM_1:PWMUDB:status_0\/q |
\PWM_1:PWMUDB:genblk8:stsreg\/status_0 |
1.509 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell7 |
U(0,0) |
1 |
\PWM_1:PWMUDB:status_0\ |
\PWM_1:PWMUDB:status_0\/clock_0 |
\PWM_1:PWMUDB:status_0\/q |
1.250 |
Route |
|
1 |
\PWM_1:PWMUDB:status_0\ |
\PWM_1:PWMUDB:status_0\/q |
\PWM_1:PWMUDB:genblk8:stsreg\/status_0 |
2.259 |
statusicell1 |
U(0,0) |
1 |
\PWM_1:PWMUDB:genblk8:stsreg\ |
|
HOLD |
-2.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\PWM_2:PWMUDB:status_0\/q |
\PWM_2:PWMUDB:genblk8:stsreg\/status_0 |
1.515 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell11 |
U(1,0) |
1 |
\PWM_2:PWMUDB:status_0\ |
\PWM_2:PWMUDB:status_0\/clock_0 |
\PWM_2:PWMUDB:status_0\/q |
1.250 |
Route |
|
1 |
\PWM_2:PWMUDB:status_0\ |
\PWM_2:PWMUDB:status_0\/q |
\PWM_2:PWMUDB:genblk8:stsreg\/status_0 |
2.265 |
statusicell2 |
U(1,0) |
1 |
\PWM_2:PWMUDB:genblk8:stsreg\ |
|
HOLD |
-2.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\PWM_2:PWMUDB:prevCompare1\/q |
\PWM_2:PWMUDB:status_0\/main_0 |
3.475 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell9 |
U(1,0) |
1 |
\PWM_2:PWMUDB:prevCompare1\ |
\PWM_2:PWMUDB:prevCompare1\/clock_0 |
\PWM_2:PWMUDB:prevCompare1\/q |
1.250 |
Route |
|
1 |
\PWM_2:PWMUDB:prevCompare1\ |
\PWM_2:PWMUDB:prevCompare1\/q |
\PWM_2:PWMUDB:status_0\/main_0 |
2.225 |
macrocell11 |
U(1,0) |
1 |
\PWM_2:PWMUDB:status_0\ |
|
HOLD |
0.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\PWM_1:PWMUDB:runmode_enable\/q |
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 |
3.478 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell6 |
U(0,0) |
1 |
\PWM_1:PWMUDB:runmode_enable\ |
\PWM_1:PWMUDB:runmode_enable\/clock_0 |
\PWM_1:PWMUDB:runmode_enable\/q |
1.250 |
Route |
|
1 |
\PWM_1:PWMUDB:runmode_enable\ |
\PWM_1:PWMUDB:runmode_enable\/q |
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 |
2.228 |
datapathcell1 |
U(0,0) |
1 |
\PWM_1:PWMUDB:sP8:pwmdp:u0\ |
|
HOLD |
0.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\PWM_2:PWMUDB:runmode_enable\/q |
\PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 |
3.479 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell10 |
U(1,0) |
1 |
\PWM_2:PWMUDB:runmode_enable\ |
\PWM_2:PWMUDB:runmode_enable\/clock_0 |
\PWM_2:PWMUDB:runmode_enable\/q |
1.250 |
Route |
|
1 |
\PWM_2:PWMUDB:runmode_enable\ |
\PWM_2:PWMUDB:runmode_enable\/q |
\PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 |
2.229 |
datapathcell2 |
U(1,0) |
1 |
\PWM_2:PWMUDB:sP8:pwmdp:u0\ |
|
HOLD |
0.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\PWM_1:PWMUDB:prevCompare1\/q |
\PWM_1:PWMUDB:status_0\/main_0 |
3.482 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell5 |
U(0,0) |
1 |
\PWM_1:PWMUDB:prevCompare1\ |
\PWM_1:PWMUDB:prevCompare1\/clock_0 |
\PWM_1:PWMUDB:prevCompare1\/q |
1.250 |
Route |
|
1 |
\PWM_1:PWMUDB:prevCompare1\ |
\PWM_1:PWMUDB:prevCompare1\/q |
\PWM_1:PWMUDB:status_0\/main_0 |
2.232 |
macrocell7 |
U(0,0) |
1 |
\PWM_1:PWMUDB:status_0\ |
|
HOLD |
0.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb |
\PWM_1:PWMUDB:genblk8:stsreg\/status_2 |
3.501 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
datapathcell1 |
U(0,0) |
1 |
\PWM_1:PWMUDB:sP8:pwmdp:u0\ |
\PWM_1:PWMUDB:sP8:pwmdp:u0\/clock |
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb |
3.270 |
Route |
|
1 |
\PWM_1:PWMUDB:tc_i\ |
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb |
\PWM_1:PWMUDB:genblk8:stsreg\/status_2 |
2.231 |
statusicell1 |
U(0,0) |
1 |
\PWM_1:PWMUDB:genblk8:stsreg\ |
|
HOLD |
-2.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 |
Net_35/main_0 |
4.312 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
controlcell1 |
U(0,0) |
1 |
\PWM_1:PWMUDB:genblk1:ctrlreg\ |
\PWM_1:PWMUDB:genblk1:ctrlreg\/clock |
\PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 |
2.040 |
Route |
|
1 |
\PWM_1:PWMUDB:control_7\ |
\PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 |
Net_35/main_0 |
2.272 |
macrocell2 |
U(0,0) |
1 |
Net_35 |
|
HOLD |
0.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 |
\PWM_1:PWMUDB:runmode_enable\/main_0 |
4.312 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
controlcell1 |
U(0,0) |
1 |
\PWM_1:PWMUDB:genblk1:ctrlreg\ |
\PWM_1:PWMUDB:genblk1:ctrlreg\/clock |
\PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 |
2.040 |
Route |
|
1 |
\PWM_1:PWMUDB:control_7\ |
\PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 |
\PWM_1:PWMUDB:runmode_enable\/main_0 |
2.272 |
macrocell6 |
U(0,0) |
1 |
\PWM_1:PWMUDB:runmode_enable\ |
|
HOLD |
0.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\PWM_2:PWMUDB:genblk1:ctrlreg\/control_7 |
\PWM_2:PWMUDB:runmode_enable\/main_0 |
4.619 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
controlcell2 |
U(1,0) |
1 |
\PWM_2:PWMUDB:genblk1:ctrlreg\ |
\PWM_2:PWMUDB:genblk1:ctrlreg\/clock |
\PWM_2:PWMUDB:genblk1:ctrlreg\/control_7 |
2.040 |
Route |
|
1 |
\PWM_2:PWMUDB:control_7\ |
\PWM_2:PWMUDB:genblk1:ctrlreg\/control_7 |
\PWM_2:PWMUDB:runmode_enable\/main_0 |
2.579 |
macrocell10 |
U(1,0) |
1 |
\PWM_2:PWMUDB:runmode_enable\ |
|
HOLD |
0.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|